AS/NZS 62386.101:2024
Digital addressable lighting interface, Part 101: General requirements - System components.
Standard identically adopts IEC 62386 101:2022, which specifies system components in a bus system for control by digital signals of electronic lighting equipment.
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AS/NZS 62386.101:2024 Digital addressable lighting interface General requirements - System components (IEC 62386-101:2022, MOD)
Preface
FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Terms and definitions
4 General
4.1 Purpose
4.2 Version number
4.3 System structure and architecture
4.4 System information flow
4.5 Command types
4.6 Bus units
4.6.1 Transmitters and receivers in bus units
4.6.2 Control gear
4.6.3 Input device
4.6.4 Single-master application controller
4.6.5 Multi-master application controller
4.6.6 Sharing an interface
4.6.7 Power for operation
4.7 Bus power supply and load calculations
4.7.1 Current demand coverage
4.7.2 Maximum signal current compliance
4.7.3 Simplified system calculation
4.8 Wiring
4.8.1 Wiring structure
4.8.2 Wiring specification
4.9 Electrical safety requirements
4.9.1 General
4.9.2 Insulation
4.9.3 Electric strength
4.9.4 Limitation of the touch current from the device to the bus
4.10 Earthing of the bus
4.11 Power interruptions at bus units
4.11.1 Different levels of power interruptions
4.11.2 Short power interruptions of external power supply
4.11.3 External power cycle
4.11.4 Short interruptions of bus power supply
4.11.5 Bus power down
4.11.6 System start-up timing
5 Electrical specification
5.1 General
5.2 Marking of the interface
5.3 Capacitors between the interface and earth
5.4 Signal voltage rating
5.5 Signal current rating
5.6 Marking of bus powered bus unit
5.7 Signal rise time and fall time
6 Bus power supply
6.1 General
6.2 Marking of the bus power supply terminals
6.3 Capacitors between the interface and earth
6.4 Voltage rating
6.5 Current rating
6.5.1 General current rating
6.5.2 Single bus power supply current rating
6.5.3 Integrated bus power supply current rating
6.5.4 Dynamic behaviour of the bus power supply
6.6 Bus power supply timing requirements
6.6.1 Short power supply interruptions
6.6.2 Short circuit behaviour
7 Transmission protocol structure
7.1 General
7.2 Bit encoding
7.2.1 Start bit and data bit encoding
7.2.2 Stop condition encoding
7.3 Frame description
7.4 Frame types
7.4.1 16-bit forward frame
7.4.2 24-bit forward frame
7.4.3 32-bit forward frame
7.4.4 Reserved forward frame
7.4.5 Backward frame
7.4.6 Proprietary forward frames
8 Timing
8.1 Single-master transmitter timing
8.1.1 Single-master transmitter bit timing
8.1.2 Single-master transmitter frame sequence timing
8.2 Receiver timing
8.2.1 Receiver bit timing
8.2.2 Receiver bit timing violation
8.2.3 Receiver frame size violation
8.2.4 Receiver frame sequence timing
8.2.5 Reception of backward frames
8.3 Multi-master transmitter timing
8.3.1 Multi-master transmitter bit timing
8.3.2 Multi-master transmitter frame sequence timing
9 Method of operation
9.1 Dealing with frames and commands
9.1.1 General
9.1.2 Frame received or rejected
9.1.3 Frame accepted or ignored
9.1.4 Command accepted or ignored
9.1.5 Command executed or discarded
9.2 Collision avoidance, collision detection and collision recovery
9.2.1 General
9.2.2 Collision avoidance
9.2.3 Collision detection
9.2.4 Collision recovery
9.3 Transactions
9.4 Send-twice forward frames and send-twice commands
9.5 Command iteration
9.6 Usage of a shared interface
9.6.1 General
9.6.2 Backward frames
9.6.3 Forward frames
9.7 Use of multiple bus power supplies
10 Declaration of variables
11 Definition of commands
Annex A (informative) Background information for systems
Annex B (informative) Touch current
Bibliography
Appendix ZZ (normative) Modifications to IEC 62386‑101:2022 for Australia
Figure 1 — IEC 62386 graphical overview
Figure 2 — System structure example
Figure 3 — Communication between bus units (example)
Figure 4 — Example of a shared interface
Figure 5 — Start-up timing example
Figure 6 — Maximum signal rise and fall time measurements
Figure 7 — Minimum signal rise and fall time measurements
Figure 8 — Bus power supply current behaviour
Figure 9 — Bus power supply voltage behaviour
Figure 10 — Frame example
Figure 11 — Bi-phase encoded bits
Figure 12 — Bit timing example
Figure 13 — Settling time illustration
Figure 14 — Receiver timing decision example
Figure 15 — Dealing with frames and commands
Figure 16 — Collision detection timing decision example
Figure 17 — Collision recovery example
Figure A.1 — Single-master architecture example
Figure A.2 — Multi-master architecture example with one application controller
Figure A.3 — Multi-master architecture example with two application controllers
Figure A.4 — Multi-master architecture example with integrated input device
Figure A.5 — Multi-master architecture example with integrated input device and bus power supply
Figure A.6 — Collision detection timing diagram
Figure A.7 — Transmitter and receiver timing illustration
Figure A.8 — Bus power supply current values
Figure A.9 — Current demand coverage
Figure A.10 — Combination of four bus power supplies
Figure A.11 — Redundant bus power supplies
Figure B.1 — Touch current from a bus unit
Figure B.2 — Summation of touch currents from several bus units
Table 1 — System components
Table 2 — Transmitters and receivers in bus units
Table 3 — Power-interruption timing of external power
Table 4 — Power-interruption timing of bus power
Table 5 — Short power interruptions
Table 6 — Start-up timing
Table 7 — System voltage levels
Table 8 — Receiver voltage levels
Table 9 — Transmitter voltage levels
Table 10 — Current rating
Table 11 — Signal rise and fall times
Table 12 — Bus power supply output voltage
Table 13 — Bus power supply current rating
Table 14 — Bus power supply dynamic behaviour
Table 15 — Short circuit timing behaviour
Table 16 — Transmitter bit timing
Table 17 — Transmitter settling time values
Table 18 — Receiver timing starting at the beginning of a logical bit
Table 19 — Receiver timing starting at an edge inside of a logical bit
Table 20 — Receiver settling time values
Table 21 — Multi-master transmitter bit timing
Table 22 — Multi-master transmitter settling time values
Table 23 — Checking a logical bit, starting at an edge at the beginning of the bit
Table 24 — Checking a logical bit, starting at an edge inside the bit
Table 25 — Collision recovery timing
Table 26 — Transmitter command iteration timing
Table 27 — Receiver command iteration timing
Table A.1 — Maximum cable length
Table A.2 — OSI layer model of the IEC 62386 series
Table A.3 — Effects of combining version number 1 and version number 2.y devices
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AS/NZS 62386.101:2024 Digital addressable lighting interface General requirements - System components (IEC 62386-101:2022, MOD)
Preface
FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Terms and definitions
4 General
4.1 Purpose
4.2 Version number
4.3 System structure and architecture
4.4 System information flow
4.5 Command types
4.6 Bus units
4.6.1 Transmitters and receivers in bus units
4.6.2 Control gear
4.6.3 Input device
4.6.4 Single-master application controller
4.6.5 Multi-master application controller
4.6.6 Sharing an interface
4.6.7 Power for operation
4.7 Bus power supply and load calculations
4.7.1 Current demand coverage
4.7.2 Maximum signal current compliance
4.7.3 Simplified system calculation
4.8 Wiring
4.8.1 Wiring structure
4.8.2 Wiring specification
4.9 Electrical safety requirements
4.9.1 General
4.9.2 Insulation
4.9.3 Electric strength
4.9.4 Limitation of the touch current from the device to the bus
4.10 Earthing of the bus
4.11 Power interruptions at bus units
4.11.1 Different levels of power interruptions
4.11.2 Short power interruptions of external power supply
4.11.3 External power cycle
4.11.4 Short interruptions of bus power supply
4.11.5 Bus power down
4.11.6 System start-up timing
5 Electrical specification
5.1 General
5.2 Marking of the interface
5.3 Capacitors between the interface and earth
5.4 Signal voltage rating
5.5 Signal current rating
5.6 Marking of bus powered bus unit
5.7 Signal rise time and fall time
6 Bus power supply
6.1 General
6.2 Marking of the bus power supply terminals
6.3 Capacitors between the interface and earth
6.4 Voltage rating
6.5 Current rating
6.5.1 General current rating
6.5.2 Single bus power supply current rating
6.5.3 Integrated bus power supply current rating
6.5.4 Dynamic behaviour of the bus power supply
6.6 Bus power supply timing requirements
6.6.1 Short power supply interruptions
6.6.2 Short circuit behaviour
7 Transmission protocol structure
7.1 General
7.2 Bit encoding
7.2.1 Start bit and data bit encoding
7.2.2 Stop condition encoding
7.3 Frame description
7.4 Frame types
7.4.1 16-bit forward frame
7.4.2 24-bit forward frame
7.4.3 32-bit forward frame
7.4.4 Reserved forward frame
7.4.5 Backward frame
7.4.6 Proprietary forward frames
8 Timing
8.1 Single-master transmitter timing
8.1.1 Single-master transmitter bit timing
8.1.2 Single-master transmitter frame sequence timing
8.2 Receiver timing
8.2.1 Receiver bit timing
8.2.2 Receiver bit timing violation
8.2.3 Receiver frame size violation
8.2.4 Receiver frame sequence timing
8.2.5 Reception of backward frames
8.3 Multi-master transmitter timing
8.3.1 Multi-master transmitter bit timing
8.3.2 Multi-master transmitter frame sequence timing
9 Method of operation
9.1 Dealing with frames and commands
9.1.1 General
9.1.2 Frame received or rejected
9.1.3 Frame accepted or ignored
9.1.4 Command accepted or ignored
9.1.5 Command executed or discarded
9.2 Collision avoidance, collision detection and collision recovery
9.2.1 General
9.2.2 Collision avoidance
9.2.3 Collision detection
9.2.4 Collision recovery
9.3 Transactions
9.4 Send-twice forward frames and send-twice commands
9.5 Command iteration
9.6 Usage of a shared interface
9.6.1 General
9.6.2 Backward frames
9.6.3 Forward frames
9.7 Use of multiple bus power supplies
10 Declaration of variables
11 Definition of commands
Annex A (informative) Background information for systems
Annex B (informative) Touch current
Bibliography
Appendix ZZ (normative) Modifications to IEC 62386‑101:2022 for Australia
Figure 1 — IEC 62386 graphical overview
Figure 2 — System structure example
Figure 3 — Communication between bus units (example)
Figure 4 — Example of a shared interface
Figure 5 — Start-up timing example
Figure 6 — Maximum signal rise and fall time measurements
Figure 7 — Minimum signal rise and fall time measurements
Figure 8 — Bus power supply current behaviour
Figure 9 — Bus power supply voltage behaviour
Figure 10 — Frame example
Figure 11 — Bi-phase encoded bits
Figure 12 — Bit timing example
Figure 13 — Settling time illustration
Figure 14 — Receiver timing decision example
Figure 15 — Dealing with frames and commands
Figure 16 — Collision detection timing decision example
Figure 17 — Collision recovery example
Figure A.1 — Single-master architecture example
Figure A.2 — Multi-master architecture example with one application controller
Figure A.3 — Multi-master architecture example with two application controllers
Figure A.4 — Multi-master architecture example with integrated input device
Figure A.5 — Multi-master architecture example with integrated input device and bus power supply
Figure A.6 — Collision detection timing diagram
Figure A.7 — Transmitter and receiver timing illustration
Figure A.8 — Bus power supply current values
Figure A.9 — Current demand coverage
Figure A.10 — Combination of four bus power supplies
Figure A.11 — Redundant bus power supplies
Figure B.1 — Touch current from a bus unit
Figure B.2 — Summation of touch currents from several bus units
Table 1 — System components
Table 2 — Transmitters and receivers in bus units
Table 3 — Power-interruption timing of external power
Table 4 — Power-interruption timing of bus power
Table 5 — Short power interruptions
Table 6 — Start-up timing
Table 7 — System voltage levels
Table 8 — Receiver voltage levels
Table 9 — Transmitter voltage levels
Table 10 — Current rating
Table 11 — Signal rise and fall times
Table 12 — Bus power supply output voltage
Table 13 — Bus power supply current rating
Table 14 — Bus power supply dynamic behaviour
Table 15 — Short circuit timing behaviour
Table 16 — Transmitter bit timing
Table 17 — Transmitter settling time values
Table 18 — Receiver timing starting at the beginning of a logical bit
Table 19 — Receiver timing starting at an edge inside of a logical bit
Table 20 — Receiver settling time values
Table 21 — Multi-master transmitter bit timing
Table 22 — Multi-master transmitter settling time values
Table 23 — Checking a logical bit, starting at an edge at the beginning of the bit
Table 24 — Checking a logical bit, starting at an edge inside the bit
Table 25 — Collision recovery timing
Table 26 — Transmitter command iteration timing
Table 27 — Receiver command iteration timing
Table A.1 — Maximum cable length
Table A.2 — OSI layer model of the IEC 62386 series
Table A.3 — Effects of combining version number 1 and version number 2.y devices
Previous versions
AS/NZS 62386.101:2024
Online Library subscription information
Online library subscriptions provide a cost-effective solution for organisations of any size to access the latest standards, offering 24/7 access to a personalised catalogue. The service ensures subscribers have have the most up-to-date version of selected standards, incluing automatic updates for any amendments or versions. Pricing is dependent on the chosen standards and the number of concurrent users, with discounts applied from the standards PDF price. For customised subscriptions or further inquiries, contact the Online Library team.